1. Technical Field
Various embodiments of the present disclosure may generally relate to a sensing buffer, peripheral circuit, or memory device, and more particularly to a peripheral circuit or memory device including a sensing buffer.
2. Related Art
A NAND flash memory device may include a memory cell array for storing data, peripheral circuits for performing a program operation, a read operation and a delete operation. The NAND flash memory device may also include a control logic for controlling the peripheral circuit in response to a command.
The memory cell array may include a plurality of planes. Each plane may include a plurality of memory blocks. Each memory block may include a plurality of strings. Each string may include a plurality of memory cells for storing the data.
A peripheral circuit may include a voltage generating circuit, a row decoder, a page buffer unit, a column decoder and an input-output circuit. A voltage generating circuit generates a variety of operating voltages. The row decoder transmits the operating voltage to a selected memory block, among a plurality of memory blocks. The page buffer unit is coupled to the memory cell array via bit lines and temporarily stores the data. The column decoder performs data transfer between the input-output circuit and the page buffer unit. The input-output circuit transmits the data, the command and an address between a controller and the memory device.
The control logic controls the memory device in response to a command received from a host, or transmits data read from the memory device to the host.